THE EFFECTS OF NANO-METER PROCESS TECHNOLOGIES ON DIGITAL CIRCUIT DESIGN FLOW

Abstract

With the continuous development of today's technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure after fabrication. In the digital domain both timing and power performance of integrated circuits are increasingly affected by proximity effects. Therefore, it is mandatory to take into account such effects during digital cell characterization accurately to capture the process variations and hence generating more precise timing models. The more accurate modeling of all digital cell variations, the less value of defined On Chip Variation (OCV) specifically in recent technologies. Reducing OCV value leads to more relaxed timing constraints and hence, less power, smaller area and shorter design cycle. This work presents a proposal for a design flow to enhance the manufacturability of the traditional standard cell library. The novel method comprises fully automated proximity-aware techniques to measure timing variations in digital cells. The new proposed flow is examined on 45 nm recent technologies and results indicate a ±6% variation across whole library contexts with respect to mean value.This shows the importance of having a variability-aware method that qualifies the libraries to be adopted for circuit designs.