The Effects of using Multiple Patterning Techniques on Electronic Circuits Design

Abstract

Multiple Patterning Techniques (MPT) are the only promising solutions that will enable the fabrication of electronic circuits in the sub-20nm technology nodes. The thesis aims to study the effect of using such techniques in fabrication on electronic circuit design. It also aims to seek solutions at the design phase that can make the final design less sensitive to variations imposed by MPT. The thesis is divided into five chapters, in addition to lists of contents, tables and figures as well as list of references and one appendix. Keywords Lithography, Multiple Patterning, Overlay Error, Capacitance Variation, CAD. Chapter 1 This chapter briefly introduces the motivation of having MPT in the current state-of-the-art Integrated Circuits (ICs) industry. While MPT is not the only solution available to print shapes on wafer, which couldn’t be resolved with conventional lithography, the chapter shows why MPT is the preferred solution that is highly adopted by all chip makers in the new technology nodes. The chapter ends with a brief preview of the thesis contents. Chapter 2 The chapter describes the physical limits of lithography- the key player in High Volume Manufacturing (HVM) of integrated circuits. The Rayleigh criterion quantifying this limit is discussed, justifying the necessity of having other innovative solutions like Multiple Patterning Techniques (MPT) as the state-of-the-art solution in Integrated Circuits (IC) industry. This chapter also introduces the different types of Multiple Patterning Techniques available for use by the leading Integrated Devices Manufacturers (IDM). It describes the fabrication process associated with each one of them, stating their advantages and disadvantages. The chapter ends by listing previous work related to the study of MPT effects. Chapter 3 This chapter discusses the impact imposed by MPT on the current design flow of ICs. The effect on physical design phases like the Design Rule Compliance (DRC) phase, and Parasitic Extraction (PEX) phase are demonstrated in more details. The chapter discusses also the electrical impact that the schematics designer should be aware of, as a result of processing one design layer with MPT. Chapter 4 The Chapter provides the description of the experiment used as a case study for MPT effects. The details of the circuit schematics, circuit layout, and Process Design Kit (PDK) used for the case study are demonstrated. The methodology used to evaluate the performance impact of MPT on a ring oscillator circuit (chosen as the circuit under test), along with the results, is provided too. Chapter 5 This chapter has more insight of how the design should take care of the MPT effect, using a worst-case scenario methodology. More than one solution is provided on the schematics design scale and the layout design scale. Analysis of each solution and its overall impact on the circuit performance is described in details. The thesis ends by summary, and future work.