CAD for 3D Integration - Static Timing Analysis (3D-STA)

Abstract

3D integration presents a paradigm shift that will enable larger cell integration, through the stacking of multiple layers (tiers)using bonding and Through Silicon Vias (TSVs). 3D integration introduces several benefits in delay areas and foot print.

The use of three dimensional chip fabrication technologies has emerged as a solutionfor the difficulties related to the continuous scaling of bulk silicon devices. Although thetechnology already exists, it is undervalued and underutilized largely due to the design and verification challenges that a complex 3D design presents.

CAD tools that are capable of dealing with 3D integrated circuits are still under development. In this work a proposed Static Timing Analysis (STA) toolis presented with a new technique to handle effectively 3D integration with minimum modifications. In addition, a proposed simplified lumped model for TSV is also presented andhas been inserted into the framework delay calculations.

The proposed 3DIC timing verification tool serves as an efficient mean to perform all setup and hold timing checks, in which the multi-die design will not be transformed to appear as a traditional 2D design in verification purposes.