All Digital Phase Locked Loop

Abstract

All-digital phase-locked loop (ADPLL) has recently drawn a significant research attention as the technology paradigm shifts into the nanometer CMOS arena. By replacing a bulky passive loop filter by a more cost effective digital filter and circumvent- ing the need for high-performance charge pump circuitry, AD- PLL offers many advantages over classical charge pump PLL. Moreover, it offers the benefits of digital circuits including broad programmability and testability, noise immunity, and enhanced robustness to process, voltage, and temperature (PVT) varia- tions. Recently, Σ∆ Fractional-N ADPLL, which is based on time-to-digital converter (TDC), showed its ability to be used as a frequency synthesizer and meeting the stringent wireless

communication specifications. However, designing it with a wide bandwidth and low in-band and out-of-band phase noise is chal- lenging. In general, the in-band phase noise of Σ∆ Fractional-N TDC-based ADPLL is limited by TDC resolution whereas its out-of-band phase noise is limited by Σ∆ quantization noise. Several techniques have been proposed in literature to en- hance TDC resolution. Among these is gated-ring oscillator TDC (GRO-TDC) architecture which achieves sub-ps resolution by pushing the power of quantization noise with first-order noise- shaping functionality. However, GRO-TDC is susceptible to ana- log circuit imperfections such as skew error and dead-zone. More- over, GRO-TDC suffers from high power consumption. There are two main goals of this thesis. The first one is to design a second-order noise-shaping TDC that achieves sub-ps resolution and overcome the analog circuit imperfection of GRO- TDC. The other goal is to design a fractional-N TDC-based AD- PLL, that leverages this high-resolution TDC and an existing digital technique to cancel Σ∆ quantization noise, in order to implement a low-noise wide-bandwidth digital frequency synthe- sizer. Firstly, the thesis presents a new TDC architecture that relies on oversampling and second-order noise-shaping to achieve sub-ps resolution. The proposed TDC, which is based on switched-ring oscillator (SRO), is used to overcome the GRO-TDC performance limitations. Simulation results using 130 nm CMOS process show that the effective TDC resolution in 1 MHz, 5 MHz and 10 MHz bandwidths are 157 fs, 271 fs, and 375 fs, respectively while con-

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suming 1.7 mW from 1.2 V supply. It is worth to mention that the proposed TDC architecture can be used in many applications other than ADPLLs. Secondly, an Σ∆ fractional-N ADPLL, which is based on second-order noise-shaping TDC, is introduced. The system de- sign shows that the in-band phase noise is not limited by TDC resolution. Simulation Results showed that the in-band phase noise in 920 kHz bandwidth is -115 dBc/Hz. Moreover, the sim- ulated integrated RMS jitter is about 160 fs which is the lowest achieved one among other TDC-based ADPLL architectures in literature. The proposed ADPLL architecture consumes 21.5 mW from 1.2 V supply while achieving a jitter figure of merit (F OMJ ) of -243 dB which the best one comparing to state-of-the-art sys- tems.