VHDL Synthesis for ASICs Applied to DLX RISC Processors

Abstract

The application of ASIC design steps starting with VHDL synthesis and ending with layout generation is presented in this thesis. The DLXS processor, which is a modified and unpipelined version of the 32-bit DLX RISC processor, is taken - as a case stndy - to build in order to prove that complex designs can be accomplished with VHDL synthesis. To prove validation of the "VHDL synthesis for AS!Cs" technique, a modified 8- bit version of the ALU of the DLXS processor is targeted for fabrication with the CMOS 1.2fl technology. The CMOSN standard cell library is used in the phases of synthesis, simulation and layout generation. The ALU chip layout is saved in the CIF format and sent for fabrication through the MOSIS service with the AMI ABN 1.2fl CMOS process. The thesis is organized as follows: Chapter one Presents an introduction to VLSI Design techniques, and Mentor Graphics EDA tools used in ASIC design.

Chapter two Presents a survey on synthesis and optimization, including synthesis classification, pros _..._ and cons of synthesis, VHDL synthesizable subset for AutoLogic II, and synthesis procedures followed by the AutoLogic II synthesis tool.