Layout Automation of Analog Integrated Circuits

Abstract

This thesis discusses an overview on the analog layout design challenges in deep sub-micron processes and the impact of time and effort needed to accomplish retargeted analog circuit. State of the art in analog layout placement retargeting automation flows is presented, as well as an automated analog layout placement retargeting flow based on Satisfiability Modulo Theories (SMT) are proposed. Finally, real design examples are used to demonstrate the flow proposal. This thesis is divided into five chapters including lists of contents, tables and figures as well as list of references and one appendix: Chapter 1 This chapter provides an overview on the analog layout retargeting challenges. Motivation, objective and contributions of this work are illustrated. Also, the organization of the thesis is highlighted. Chapter 2 This chapter discusses the analog design flow as well as analog design retargeting. State of the art is discussed and finally the SMT based analog placer that has been employed in this work has been discussed. Chapter 3 An analog layout retargeting placement flow based on Satisfiability Modulo Theories analog placer is proposed. The flow considerations, a step by step introduction to the proposed flow and the flow architecture are discussed. Chapter 4 This chapter provides a demonstration of layout placements obtained for the two real designs examples using the proposed flow. The results and final achieved layouts are shown as well as comparison to previous flows performance. Finally, a discussion on the results and highlights on the benefits of the proposed flow are discussed. Chapter 5 This chapter concludes the work presented in this thesis, and highlights the proposed future work.