Design of a Digital-Output Capacitive Sensor Interface

Abstract

This work presents a novel energy-efficient capacitance-to-digital con- verter (CDC) interface for capacitive pressure sensors. A new direct-capacitance- comparison technique (DCCT) is proposed and employed together with a successive approximation register (SAR) algorithm to resolve the sensor ca- pacitance by, directly, comparing it to an on-chip binary-weighted capacitive DAC array (CAPDAC). This conversion technique, significantly, simplifies the process of capacitance-to-digital conversion and enables using less ana- log blocks.

The proposed interface circuit topology requires neither a high purity ref- erence clock for digital conversion, nor a bandgap reference voltage. Further- more, the interface does not have a capacitance-to-voltage converter (CTV),

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which all add up to maximize the proposed solution energy-efficiency com- pared to other pressure sensors capacitive interface architectures.

It is, also, shown that the proposed new CDC employs an offset DAC array (OFFDAC that compensates for the sensor rest and co-integration par- asitic capacitances. Therefore, the proposed CDC provides a dynamically zoomed digital-output code that corresponds to the range of the capaci- tance change only rather than sensor rest or parasitic capacitances. Also, the proposed CDC provides a very high capacitance readout linearity that ,considerably, outperforms some techniques proposed in literature.

The sensor rest, co-integration, and full-scale (FS) range capacitance can be easily adjusted using the proposed CDC. A complete system analysis shows how the power consumption and the comparator sensitivity are traded for sensor rest capacitance, the FS capacitance, and the ability to tolerate large parasitic capacitance.

The proposed 8-bit SAR-based CDC is designed and simulated using 0.18µm standard CMOS technology. For the reported power consumption, it can handle parasitic capacitance combined with rest capacitance up to four times larger than the sensor FS capacitance range. The CDC exhibits a capacitance sensing range from 4pF to 6pF, achieves a resolution and lin- earity of 7.26-bit and 8.2-bit, respectively, and a capacitance noise floor of 5.32 aF /√Hz, at 7.7µW power consumption and 36µs conversion time. The

interface circuit occupies an active area of 0.2mm2, and achieves a figure-of- merit (FoM) of 1.8pJ/step at 1.4V supply. Compared to the state-of-the-art implementations with similar performance, this solution provides a consid-

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erable enhancement.

key words: Capacitance-to-digital converter (CDC), capacitive pressure sen- sors, direct-capacitance comparison technique, successive approximation reg- ister (SAR), energy-efficient interfaces, low-power interfaces.