REALIZATION OF ARITHMATIC CIRCUITS USING SINGLE ELECTRON TRANSISTOR

Abstract

This dissertation addressed realization of arithmatic circuits using Single Electron Transistor. First, the design and simulation of SET logic gate and circuits was presented. Moreover, a simple structure of some logic gate was presented. Second, a through review of many designs of SET full adders (FAs) was carried out that has allowed a better understanding of their advantages and disadvantages. The comparison between these FAs included their power • dissipation, output swing, number of component, and complexity design. Finally, multibit threshold adder and simulation results for 8-bit adder were presented. All the simulations in this dissertation were run by SET •simulator SIMON. The simulation results showed quantitatively the ultra low •power

dissipations but the major problem encountered while constructing large circuits was the very long simulation run which is typical of Monte Carlo based simulations. This could be alleviated by using SPICE simulations.. Using SPICE might have an additional advantages in reducing simulation times (comparedto Monte Carlo simulators)..