Implementation and Verification of Resolution Enhancement Techniques for Sub-Wavelength VLSI Microlithography
Mohamed Sayed Yehia Bahnas;
Abstract
The scope of the presented Thesis is mainly: Survey on the
VLSI Microlithography process flow, and reporting the faced
challenges in the sub-100nm technologies manufacturing.
Analysis and implementation of several types of Resolution
Enhancement Techn
VLSI Microlithography process flow, and reporting the faced
challenges in the sub-100nm technologies manufacturing.
Analysis and implementation of several types of Resolution
Enhancement Techn
Other data
| Title | Implementation and Verification of Resolution Enhancement Techniques for Sub-Wavelength VLSI Microlithography | Authors | Mohamed Sayed Yehia Bahnas | Keywords | Implementation and Verification of Resolution Enhancement Techniques for Sub-Wavelength VLSI Microlithography | Issue Date | 2008 | Description | The scope of the presented Thesis is mainly: Survey on the VLSI Microlithography process flow, and reporting the faced challenges in the sub-100nm technologies manufacturing. Analysis and implementation of several types of Resolution Enhancement Techn |
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