Automated and Visual Techniques for Assertion Debugging In Digital Design
Moaz Magdy Mostafa Mohamed;
Abstract
Verification is the most time consuming stage in design cycle as it takes 75% of the total design time. Many verification techniques are proposed to reduce verification time as assertion based verification. Our concern is debugging failed assertions in the simulation phase. Many debugging techniques are proposed to debug failed assertions. The currently used debugging techniques have many drawbacks as,
1- Random mutation increases debugging time.
2- Complex visual presentation is used to debug failed assertion.
This research proposes some new methodologies to debug failed concurrent and immediate assertions. We propose two new techniques to debug failed concurrent assertions and one new technique to debug failed immediate assertions. The proposed methodologies are based on a new algorithm (propagate-and-repeat), a new three-state visual representation, a new enhanced mutation model, and a new “pattern matching” model. The experimental results show that the proposed techniques can fix errors in assertions within reasonable time for different cases.
Chapter 1: This chapter presents an overview of verification. Motivation and research contribution are mentioned too in this chapter.
Chapter 2: This chapter gives background on SystemVerilog assertion. All types of assertion are described including simple immediate assertions, deferred immediate assertions, and concurrent assertions.
Chapter 3: This chapter gives a background on some currently used failed assertion debugging methodologies, which use mutation and visualization.
Chapter 4: This chapter presents the new proposed debugging methodologies. It also includes more details on the new three-state visual representation, the new propagate-and-repeat-algorithm, the new pattern matching model, and the new enhanced mutation model.
Chapter 5: This chapter shows the simulation results for all proposed methodology.
Chapter 6: This chapter includes conclusion and future results.
Key words: SVA debugging, pattern packet, results packet, three-state visual representation, propagate-and-repeat algorithm, pattern matching model.
1- Random mutation increases debugging time.
2- Complex visual presentation is used to debug failed assertion.
This research proposes some new methodologies to debug failed concurrent and immediate assertions. We propose two new techniques to debug failed concurrent assertions and one new technique to debug failed immediate assertions. The proposed methodologies are based on a new algorithm (propagate-and-repeat), a new three-state visual representation, a new enhanced mutation model, and a new “pattern matching” model. The experimental results show that the proposed techniques can fix errors in assertions within reasonable time for different cases.
Chapter 1: This chapter presents an overview of verification. Motivation and research contribution are mentioned too in this chapter.
Chapter 2: This chapter gives background on SystemVerilog assertion. All types of assertion are described including simple immediate assertions, deferred immediate assertions, and concurrent assertions.
Chapter 3: This chapter gives a background on some currently used failed assertion debugging methodologies, which use mutation and visualization.
Chapter 4: This chapter presents the new proposed debugging methodologies. It also includes more details on the new three-state visual representation, the new propagate-and-repeat-algorithm, the new pattern matching model, and the new enhanced mutation model.
Chapter 5: This chapter shows the simulation results for all proposed methodology.
Chapter 6: This chapter includes conclusion and future results.
Key words: SVA debugging, pattern packet, results packet, three-state visual representation, propagate-and-repeat algorithm, pattern matching model.
Other data
| Title | Automated and Visual Techniques for Assertion Debugging In Digital Design | Other Titles | طرق مميكنة و بصرية لتتبع و تصحيح أخطاء التأكيدات فى التصميم العددى | Authors | Moaz Magdy Mostafa Mohamed | Issue Date | 2016 |
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