Digital Calibration for Time Interleaved Analog to Digital Converter

Abstract

The pipelined time interleaved analog-to-digital converter (TIADC) has been widely used for its high speed and low complexity. This thesis studies the challenges face its implementation including the mismatches among its sub-ADCs. A digital calibration technique suitable for the pipelined TIADC is proposed to calibrate these mismatches to relax the stringent requirements of the design. The thesis starts by presenting the methods needed to model the pipelined TIADC using Matlab\\ . Then, different calibration techniques in the liter- ature are studied and presented. Finally, a technique used for calibrating pipelined TIADC mismatches is proposed. The performance results for all these techniques are evaluated using Matlab\\ . The proposed technique was implemented on a FPGA to evaluate its resources utilization. Simulation re- sults demonstrate a 40dB improvement in the measured SNDR.