ULTRA LOW POWER ANALOG TO DIGITALCONVERTER USING SUCCESSIVE APPROXIMATION REGISTER LOGICWITH VOLTAGE OFFSET CANCELLATION TECHNIQUE

Abstract

It is concluded that power is a main concern in a lot of low power applications like low power biomedical applications. Improving the efficiency of the system is a main concern, this can be done by increasing SNR of the output of the system. An offset cancellation technique for comparator is used in SAR ADC system is presented. Input referred offset of comparator in SAR ADC systems affects the total SNR of the whole system. Many techniques can be used to reduce the effect of input referred offset and any additional noise, one of these techniques is using the proposed technique that uses a preamplifier based dynamic CMOS comparator for optimization offset voltage using charge storage techniques. Simulations have been performed to determine the minimum of offset voltage. Comparing with the previous work, a realization of low offset in this system, which is compatible with SAR ADC operation. The simulation results of presented system shows that it has high performance compared with that proposed in [34] & [41]. Where the proposed SAR ADC with offset cancelation technique has less power consumption than that presented in [41] and less complexity than that in [34]. Better results have been achieved after applying the optimization technique but at the same time both the reduction techniques has large power delay product and power-delay number of transistor product. Thus high accuracy is only obtained at the expense of high energy consumption along with silicon area. Dynamic latched comparators are used due to their low power consumption as they don’t consume power in the reset mode, all the power is consumed during the regeneration mode. The value of the propagation delay is increased as the value of the supply is decreased that is because it approaches the threshold voltage of the transistors used in the design but the power consumption decreases with that decrease. Time latched comparator is mainly used to improve the figure of merit where its operation is done by comparing the widths of the periods of the signals not the amplitude of them. After simulation it is clear that type 4 comparator has the least power consumption of all the designs which equals to 227.2 pW with propagation delay 1.4 ns. The power consumed by SAR is affected mainly by two factors the supply voltage and frequency of operation. SAR logic type 2 is proposed with multiplexers inside the flip flops in order to reduce the number of D-flip flops, while non-redundant SAR is proposed in order to generate the start signal automatically through a counter. The two step SAR is proposed in order to increase the efficiency of operation. After simulation it is clear that SAR logic type 1 consumes the least power consumption which is equal to 1.213 nW.