Design of Analog VLSI Supervised-Learnable Neural Cell
Rany Amir Tawfik Gad El-Sayed;
Abstract
In this research, an analog very large-scale integration (VLSI) design of a high accuracy neural cell with supervised learning ability using standard 2 jun1 CMOS technology parameters is represented.
On the architectural level, a novel architecture is pre
On the architectural level, a novel architecture is pre
Other data
| Title | Design of Analog VLSI Supervised-Learnable Neural Cell | Other Titles | تصميم دائرة تناظريه ذات تكلمل واسع النطاق جدا لخلية عصبيه قابله للتعليم الموجه | Authors | Rany Amir Tawfik Gad El-Sayed | Keywords | Design of Analog VLSI Supervised-Learnable Neural Cell | Issue Date | 1999 | Description | In this research, an analog very large-scale integration (VLSI) design of a high accuracy neural cell with supervised learning ability using standard 2 jun1 CMOS technology parameters is represented. On the architectural level, a novel architecture is pre |
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