Clock and Data Recovery Architecture for Multi-Gigabit/ Binary links
Eliyah Wadie Ragi Kilada;
Abstract
Serial links are widely used at the peripheral of many ASIC's, specially after the
failure of parallel busses at very high speeds. The Clock and Data Recovery (CDR)
module plays an important role in any receiver, and its design is very challenging.
As
failure of parallel busses at very high speeds. The Clock and Data Recovery (CDR)
module plays an important role in any receiver, and its design is very challenging.
As
Other data
| Title | Clock and Data Recovery Architecture for Multi-Gigabit/ Binary links | Authors | Eliyah Wadie Ragi Kilada | Keywords | Clock and Data Recovery Architecture for Multi-Gigabit/ Binary links | Issue Date | 2008 | Description | Serial links are widely used at the peripheral of many ASIC's, specially after the failure of parallel busses at very high speeds. The Clock and Data Recovery (CDR) module plays an important role in any receiver, and its design is very challenging. As |
Attached Files
| File | Size | Format | |
|---|---|---|---|
| 8401EliyahKiladaThesis.V23.pdf | 99.86 kB | Adobe PDF | View/Open |
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