SUCCESSIVE APPROXIMATION REGISTER WITH CONTINUOUS DIS-ASSEMBLY ALGORITHM (SAR-CD) AND CIRCUIT DESIGN FOR TIME-BASED ANALOG TO DIGITAL CONVERTERS(TADC)

Abstract

This work proposes a novel algorithm for analog to digital conversion. The algorithm is a modified version of the successive approximation algorithm in which binary sub-weights of the input maximum are used to evaluate the corresponding digital words in a cyclic manner. The proposed algorithm moves the conditioning between the evaluated bits from the analog domain to the digital domain. In folded versions of the successive approximation ADC circuits, in which bits are evaluated in an iterative fashion, digital to analog converters may not be needed anymore. This major advantage promises for reduction in fabrication area and power consumption. A full mathematical proof for the algorithm is also introduced. A new circuit design is developed to utilize the algorithmbenefits. Results show competent power and reduction with state-of-art designs.