A Low-Power Clocking Scheme for Multi-Standard Serial Links

Abstract

This thesis presents system and circuit design for ultra-low power clock generation to be used in a multi-standard serial link transceiver. Clock generation using a phase-locked-loop (PLL) should consume less than 1.25 pJ/bit for the different supported standards. Also, the RMS-generated jitter should not exceed 0.5 psec to meet the standards requirements. The implementation is driven by the market needs in the industry to achieve multiple standards compliance in one transceiver. This imposes new design and optimization challenges that are difficult to meet, especially for some conflicting standard requirements. Also, it is necessary to reduce the power consumption to deliver the required performance while reducing power costs to extend the battery life. This PLL aims to provide the required quadrature-clock phases for the wide range of Gbps data rates to be supported, and provide spread-spectrum clocking for EMI reduction in some standards. System-level design of the proposed wide-tuning-range low-jitter PLL has been introduced. Modified circuit techniques have been implemented to reduce the power consumption without affecting the random-generated jitter and sacrificing the overall system performance. Low-power oscillator, and charge pump circuits operating at low-supply voltages are proposed. A new charge steering PLL concept is proposed that can be used for ultra-low power applications on the nm technology nodes. The PLL was implemented in two CMOS technology nodes (65-nm, and 28-nm). It can operate from 1.5 Gbps up to 12 Gbps data rate to cover SATA generations 1–3, PCIe 1–3, USB Superspeed and Superspeed+, and MIPI MPHY G1 – G4 with a random generated jitter of 0.5 ps or less, and easy programmability while consuming very-low power. The thesis is divided into six chapters including lists of contents, tables and figures as well as list of references.