High Performance Analog to Digital Converters
Michael Sherif Sobhy Nagib;
Abstract
This thesis presented the design and implementation of a power-efficient 12-bit/20-40MSPS SAR analog-to-digital converter for low-power hand-held electronics applications such as LTE, WiMAX, 802.11 a/b/g wireless com- munication and digital TV applications.
The ADC design started by exploring and studying the different options for implementing the SAR ADC feedback-DAC, timing-sequence and digital logic with the main aim of reducing the overall power consumption of the ADC. Wrapping up this study with a top-level architecture definition and budgeting specifications across the different building blocks, followed by the complete transistor-level implementation of the different building blocks of the converter in a 0.13µm/1.2V technology.
A top-down design methodology has been adopted to initially build-up and verify the complete converter through developing VHDL-AMS models for the different sub-blocks and verifying the behavioral functionality and operation of the converter, followed by a bottom-up verification of the transistor-level implementation of the different sub-blocks within the complete system. The top-down design methodology and the pin-accurate behavioral models en- abled assessing different system-level trade-offs , assumptions and decisions early within the design process.
185
The ADC design started by exploring and studying the different options for implementing the SAR ADC feedback-DAC, timing-sequence and digital logic with the main aim of reducing the overall power consumption of the ADC. Wrapping up this study with a top-level architecture definition and budgeting specifications across the different building blocks, followed by the complete transistor-level implementation of the different building blocks of the converter in a 0.13µm/1.2V technology.
A top-down design methodology has been adopted to initially build-up and verify the complete converter through developing VHDL-AMS models for the different sub-blocks and verifying the behavioral functionality and operation of the converter, followed by a bottom-up verification of the transistor-level implementation of the different sub-blocks within the complete system. The top-down design methodology and the pin-accurate behavioral models en- abled assessing different system-level trade-offs , assumptions and decisions early within the design process.
185
Other data
| Title | High Performance Analog to Digital Converters | Other Titles | المحولات التماثلية الرقمية عالية الأداء | Authors | Michael Sherif Sobhy Nagib | Issue Date | 2014 |
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