Layout Proximity Effects for Analog Design

Abstract

This thesis aims at introducing a proposed automatic flow for mitigating Layout Dependent Effect “LDE”. Among the LDE effects appearing in deep submicron technologies there is an important LDE effect called Shallow Trench Isolation (STI). These effects can’t be seen explicitly in the PEX and post layout simulations but only a change in circuit behavior can be deduced as a result from these effects. So in order to see these effects the chip needs to be fabricated then doing some measure-ments to judge correctly what the reason for the problem in this chip is. This also due to the fact of not having solid models for these effects, but all the efforts done in this field depend on some observations and developing empirical equations. Analog layout is an exhausting and time consuming task, so several analog layout automation techniques have been invented to shorten the time to market like what is happening in the digital side in which all the flow is done in an automatic way. Each invented automatic technique is created to automate a certain stage in the analog lay-out flow, this is because there are several specifications need to be satisfied in the lay-out