FPGA Application in Digital Circuit

Abstract

Increasing circuit complexity, higher performance and the demand for high quality levels is causing the industry to question currently used functional and specification based test programs. In addition, the escalating cost of production test equipment capable of measuring high performance device parameters is in many cases becoming a limiting factor. • Pseudorandom testing could be of value to digital circuits, since it does not need any effort in test generation. The pseudorandom testing methodology can also be easily applied to any class of boards u11der study, so we use this technique in our proposed system. In the proposed system the testing takes place as follow: At first the Board Under Test (BUT) will simulated to get the signature of free fault circuit and all possible faults signatures. All signatures will be stored in the FPGA, which will contain also the testing system. The proposed system used to generate random pattern. This pattern will be access to the BUT. The response will access to the proposed system to compress it by using Multiple Input Shift Register (MISR) to get signature. The signature will be compared with all signatures stored to know if the BUT is fault free or faulty and what is the fault. The result will appear on an LCD. In this thesis one chip (FPGA) is used to implement an automatic testing Equipment (ATE), implemented and tested successfully. An Altera Flex!Ok EPFIOK20RC240 chip was used in the implementation.