Switched Capacitor Voltage Converters

Abstract

The rapid advancement in CMOS technology is the main driver for consumer-based electronic devices which have a lot of features and capabilities. This advancement enables the integration of more high-speed and less-area digital circuits on the same die. However, the digital processing advancement was much faster than the battery technology advancement [Le 11] which leads the designers to use techniques like Dynamic Voltage and Frequency Scaling (DVFS) to optimally provide supply and clocking to different blocks based on need and mode of operation [Clark 01]. This forces the use of different power domains for different digital blocks. The use of large number of external power domains is not a practical solution due to limited number of package pins and the cost of using many external DC-DC converters. This leads to the importance of using on-chip DC-DC converters [Le 13, Le 15].

DC-DC converters have two main types, linear and switching regulators [Seeman 09, Breussegem 13]. The linear regulator has the advantage of simplicity and linearity but on the cost of lower efficiency compared with switching one for same difference between Vin and Vout . Switching regulators has two types. The first one is the inductor-based which has been dominating the off-chip implementations. Many research efforts have been done to fully integrate the inductors but still the integrated inductors suffer from low quality factor which affects the efficiency. The second type is the Switched-Capacitor (SC) converter which is based on the integrated high-density, low series resistance capacitors in standard CMOS process. So the SC converter has received high attention recently due to these advantages.

However, there are technical challenges in the design of fully integrated SC convert- ers. One of the most important challenges is to support a load current with wide dynamic range (e.g. load currents up to 100 mA) while keeping the output voltage ripples lower than 20 mVpp. Many techniques have been introduced to lower the level of the output voltage ripples such as phase interleaving, capacitance modula- tion, and time modulation. However, these techniques either not all-digital or can not cover a wide dynamic range of load current [Kudva 13, Le 13, Breussegem 11].

Achieving output voltage ripples lower than 20 mV for load currents up to 100 mA with integrated capacitors in an all-digital solution is still a challenging problem. Combining two or more of the already existing ripple reduction techniques may result in further reduction of output voltage ripples for a load with wide dynamic