Data Converters For High Speed Serial Links
Khaled Mohamed Ashraf Mohamed Alaa El-Din El-Gammal;
Abstract
The use of equalizers is highly needed in receivers of wired communications nowa- days. The conventional analog equalizers is efficient for low attenuation channels, as shown in the state-of-art survey. For channel attenuations, higher than 20 dB, digital equalizers are needed. Digital equalizers, provide the flexibility of imple- mentation using high number of taps, with several equalization techniques (FFE, DFE). To realize the digital equalizers, high speed ADCs are needed at the receiver front-end.
The main challenge in the ADC design, is to minimize its power consumption, such that the receiver link does not lose its power effeciency. In this thesis, a 10-Gbps 4-bit 4-channel TI-Flash ADC is presented to be used as an analog-front-end for an ADC-based-equalizer receiver-chain. Two different deisgn approaches are proposed for the implementation of the ADC, without the need for any digital calibration.
The first design approach provides a modified clocking scheme. This clocking scheme enables the use of basic topologies for ADC subblocks, and minimizes the overall ADC power consumption, achieving a F OM of 115 fJ/conversion-step. This ap- proach has some drawbacks including DN L > 1LSB which indicates one or more missing codes in the ADC I/O characteristics. These drawbacks were discussed and solved in the second design approach.
The second design approach, used the conventional clocking scheme, with pro- posed modifications in the subblocks, mainly the comparator preamplifier and the S/H. The ADC achieves IN L and DN L below 0.5LSB, achieves a F OM of 182 fJ/conversion-step, and an overall EN OB of 3.65 bits at Nyquist-rate input (5 GHz). A physical design is also proposed for the subADC. Both design approaches provide a superior F OM in comparison to the ADCs presented in the state-of-art survey.
5.2 Suggestions for Future Work
Possible extension can be made to this work as the following :
1. Implementation of a low-jitter clocking scheme for the subADCs.
2. Implementation of the bias cell to supply the different current branches, and low variation LDO.
3. Implementation of ADC reference buffer.
4. Chip fabrication and validation of the ADC, along with the equalizer to test the effeciency of this solution.
The main challenge in the ADC design, is to minimize its power consumption, such that the receiver link does not lose its power effeciency. In this thesis, a 10-Gbps 4-bit 4-channel TI-Flash ADC is presented to be used as an analog-front-end for an ADC-based-equalizer receiver-chain. Two different deisgn approaches are proposed for the implementation of the ADC, without the need for any digital calibration.
The first design approach provides a modified clocking scheme. This clocking scheme enables the use of basic topologies for ADC subblocks, and minimizes the overall ADC power consumption, achieving a F OM of 115 fJ/conversion-step. This ap- proach has some drawbacks including DN L > 1LSB which indicates one or more missing codes in the ADC I/O characteristics. These drawbacks were discussed and solved in the second design approach.
The second design approach, used the conventional clocking scheme, with pro- posed modifications in the subblocks, mainly the comparator preamplifier and the S/H. The ADC achieves IN L and DN L below 0.5LSB, achieves a F OM of 182 fJ/conversion-step, and an overall EN OB of 3.65 bits at Nyquist-rate input (5 GHz). A physical design is also proposed for the subADC. Both design approaches provide a superior F OM in comparison to the ADCs presented in the state-of-art survey.
5.2 Suggestions for Future Work
Possible extension can be made to this work as the following :
1. Implementation of a low-jitter clocking scheme for the subADCs.
2. Implementation of the bias cell to supply the different current branches, and low variation LDO.
3. Implementation of ADC reference buffer.
4. Chip fabrication and validation of the ADC, along with the equalizer to test the effeciency of this solution.
Other data
| Title | Data Converters For High Speed Serial Links | Other Titles | محولات البيانات للوصلات المتوالية فائقة السرعة | Authors | Khaled Mohamed Ashraf Mohamed Alaa El-Din El-Gammal | Issue Date | 2016 |
Attached Files
| File | Size | Format | |
|---|---|---|---|
| G12014.pdf | 308.21 kB | Adobe PDF | View/Open |
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