Power Estimation Using Emulation
Ahmed Khalil Ibrahim Abdel Haleem;
Abstract
High speed and full-system functional, timing and power consumption modeling capabilities of the developed TLM VP can provide a versatile simulation environment. This environment can be utilized not only in design space exploration, but also in SW continuous integration. As proposed in this thesis, transaction-level full-system MPSoC power estimation can be achieved at early design phases using the developed TLM virtual platform in AT simulation mode.
Total power consumption is modeled at TLM-level for various VP components. Instruction-based dynamic power consumption is specified for the processor ISS. Communication, computation and state-based dynamic power components are specified for peripheral models. In addition, static and clock tree power consumption are specified for all models. An average percentage error of 10% in power estimation at TLM-level is obtained in comparison with real HW board power consumption.
Moreover, very high speed MPSoC simulation, especially for multi-thread applications, can be reached in LT simulation mode using the TLM virtual platform that contains multi-core ISS model. An efficient ISS modeling methodology using combined TLM and DBT features can achieve fast, yet accurate, simulation speed that can reach up to 3.9X speedup over baseline QEMU which corresponds to 15% of real HW board speed. The ISS is instantiated along with fully-compliant group of SystemC TLM-2.0 models through which full-system modeling can be achieved.
6.2. Future Work
As an extension to this thesis work, communication power needs to be supported by all processor ISS components for more accurate overall power estimation. Currently only computational power is supported by the instruction-based power information. In addition, further enhancements to virtual platform performance in AT simulation mode may be performed for higher simulation speed suitable for large and complex virtual platform software emulation of hardware physical MPSoC designs.
Total power consumption is modeled at TLM-level for various VP components. Instruction-based dynamic power consumption is specified for the processor ISS. Communication, computation and state-based dynamic power components are specified for peripheral models. In addition, static and clock tree power consumption are specified for all models. An average percentage error of 10% in power estimation at TLM-level is obtained in comparison with real HW board power consumption.
Moreover, very high speed MPSoC simulation, especially for multi-thread applications, can be reached in LT simulation mode using the TLM virtual platform that contains multi-core ISS model. An efficient ISS modeling methodology using combined TLM and DBT features can achieve fast, yet accurate, simulation speed that can reach up to 3.9X speedup over baseline QEMU which corresponds to 15% of real HW board speed. The ISS is instantiated along with fully-compliant group of SystemC TLM-2.0 models through which full-system modeling can be achieved.
6.2. Future Work
As an extension to this thesis work, communication power needs to be supported by all processor ISS components for more accurate overall power estimation. Currently only computational power is supported by the instruction-based power information. In addition, further enhancements to virtual platform performance in AT simulation mode may be performed for higher simulation speed suitable for large and complex virtual platform software emulation of hardware physical MPSoC designs.
Other data
| Title | Power Estimation Using Emulation | Other Titles | تقدير الطاقة باستخدام المحاكاه | Authors | Ahmed Khalil Ibrahim Abdel Haleem | Issue Date | 2017 |
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