An Ultra-Low-Voltage Variation Tolerant SRAM Design

Abstract

This work shows methods of the design and analysis of the bitcell that allow the SRAM memory work under ultra low-voltage. To sum up, the thesis goes in a bottom-up manner, starting from the smallest building block, which is the bitcell, until it reaches the chip-level design. The thesis consists of five chapters including lists of contents, tables and figures as well as list of references and one appendix. Chapter 1: contains thesis introduction, as well as the aim of the thesis and the author contributions. Chapter 2: shows the SRAM memory architecture. It includes literature review on SRAM bitcells, literature review on write/read assist techniques, while focusing on low voltage issues that affect SRAM bitcells. Finally, it presents a full characterization of UMC-65nm technology. Chapter 3: presents the analysis automation of SRAM bitcells, followed by observations of SRAM bitcells. This leads to the SRAM bitcell design and hence the layout of a 6T SRAM bitcell. The chapter also includes modeling and implementation of write/read assist techniques, leading to a more optimized design of 6T bitcells at ultra low-voltage operation. In addition, this chapter includes comparisons between static and dynamic analysis, and analysis of the half-select issue when using wordline boosting technique for write operation. Chapter 4: presents the floorplan of the test chip. It discusses clock generation circuit design, in addition to various chip-level circuits, routing, power grid, IOs placement and packaging. Chapter 5: presents the conclusion of the thesis and the future work that can be done.