Design of Continuous Time Sigma Delta Modulator
Islam Mostafa Kamal El-Dien Hassan;
Abstract
Power supply reduction remains as one of the main challenges associated with tech- nology scaling. Technology scaling is known to improve digital circuit speed and reduce its dynamic power dissipation, which is proportional to the square of the supply value. The fact that technology scaling favors digital circuits has led to a rising trend of implementing digital-like low-voltage, inverter-based, analog circuitry.
Inverter-based implementation of operational transconductance amplifiers (OTAs) is an attractive approach for low-voltage realization of analog sub-systems. However, the high sensitivity of inverter-like amplifiers performance to process and tempera- ture variations limits the achievable performance of the whole system, across process and temperature corners. In this work, a novel process-tolerant low-voltage inverter- based OTA is proposed, to address design challenges in deep submicron technologies. A simple circuit technique to tune inverter-based, which has only two devices to the supply, amplifiers across process and temperature variations, is proposed. Hence, the variations in the amplifier DC-gain become limited and no large DC-gain vari- ations are experienced. The proposed circuit maintains the output common mode of the inverter-based amplifier, without requiring any additional voltage headroom to the simple inverter structure. The introduced technique is used to implement a third order continuous-time (CT) Σ∆ analog-to-digital converter (ADC). The main building block of the implemented ADC, is an inverter-based amplifier. This makes the resulting Σ∆ ADC easier to scale to different technology nodes.
On the system level, a third order feedforward single bit loop is implemented to have relaxed swing at the output of the integrators. First, a discrete time loop filter is implemented using MATLAB and with invariant transformation, the continuous time loop filter is driven. A SIMULINK model is implemented to check the stability and scaling of loop coefficients. Then, it is modeled using behavioral models to get each block specifications. The modulator is implemented with a 0.8 V supply which is 20% reduction of the nominal supply of the 65 nm technology. All the integrator stages are implemented as an active RC where the feedforward branches are summed together using a separate resistive feedback amplifier.
At a normalized input level of -12 dB, the modulator achieves a signal-to-noise and distortion ratio (SNDR) of 74 dB in the typical corner, while the worst case SNDR is 70 dB across all process and temperature corners, for a signal bandwidth of 64 kHz
at a sampling frequency of 6.4 MHz, while consuming 400 f1A from 0.8 V, supply,
in 65 nm CMOS technology.
Key words: low-voltage, sigma delta, scaling-friendly, inverter-based, continuous time, process variation tolerant.
Inverter-based implementation of operational transconductance amplifiers (OTAs) is an attractive approach for low-voltage realization of analog sub-systems. However, the high sensitivity of inverter-like amplifiers performance to process and tempera- ture variations limits the achievable performance of the whole system, across process and temperature corners. In this work, a novel process-tolerant low-voltage inverter- based OTA is proposed, to address design challenges in deep submicron technologies. A simple circuit technique to tune inverter-based, which has only two devices to the supply, amplifiers across process and temperature variations, is proposed. Hence, the variations in the amplifier DC-gain become limited and no large DC-gain vari- ations are experienced. The proposed circuit maintains the output common mode of the inverter-based amplifier, without requiring any additional voltage headroom to the simple inverter structure. The introduced technique is used to implement a third order continuous-time (CT) Σ∆ analog-to-digital converter (ADC). The main building block of the implemented ADC, is an inverter-based amplifier. This makes the resulting Σ∆ ADC easier to scale to different technology nodes.
On the system level, a third order feedforward single bit loop is implemented to have relaxed swing at the output of the integrators. First, a discrete time loop filter is implemented using MATLAB and with invariant transformation, the continuous time loop filter is driven. A SIMULINK model is implemented to check the stability and scaling of loop coefficients. Then, it is modeled using behavioral models to get each block specifications. The modulator is implemented with a 0.8 V supply which is 20% reduction of the nominal supply of the 65 nm technology. All the integrator stages are implemented as an active RC where the feedforward branches are summed together using a separate resistive feedback amplifier.
At a normalized input level of -12 dB, the modulator achieves a signal-to-noise and distortion ratio (SNDR) of 74 dB in the typical corner, while the worst case SNDR is 70 dB across all process and temperature corners, for a signal bandwidth of 64 kHz
at a sampling frequency of 6.4 MHz, while consuming 400 f1A from 0.8 V, supply,
in 65 nm CMOS technology.
Key words: low-voltage, sigma delta, scaling-friendly, inverter-based, continuous time, process variation tolerant.
Other data
| Title | Design of Continuous Time Sigma Delta Modulator | Other Titles | تصميم معدلات السيجما ديلتا | Authors | Islam Mostafa Kamal El-Dien Hassan | Issue Date | 2015 |
Recommend this item
Similar Items from Core Recommender Database
Items in Ain Shams Scholar are protected by copyright, with all rights reserved, unless otherwise indicated.