Low Power Frequency Loop For Multi Standard Clock and Data Recovery
Amr Abd Elhadi Abd Elhamid Abdel Hadi;
Abstract
The thesis presents a programmable PI-based CDR with new high linear PI and a digital loop filter to achieve the specifications of the jitter tolerance of multi-standard serial- links. The system is implemented in CMOS transistor level and simulated. Simulation results of different data rates are presented with the achieved standards specifications. A new proposed PI is presented herein that thesis and achieves the jitter tolerance and data rates for different standards. The PI achieves I N L of 0.2LSB and DN L of 0.15LSB and with power consumption of 2 mW drawn from 0.9v supply. The thesis is divided into seven chapters as listed below:
Other data
| Title | Low Power Frequency Loop For Multi Standard Clock and Data Recovery | Other Titles | تقنيات تصميم دوائر استعادة البيانات و التزامن متعددة المعايير منخفضة القدرة | Authors | Amr Abd Elhadi Abd Elhamid Abdel Hadi | Issue Date | 2018 |
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