Low Voltage Static Random Access Memory
Reem Sherif El Senousy Mohamed;
Abstract
Recently, with the move towards very-low power applications, Static Random Access Memories (SRAMs) are operated at very-low supply voltages to reduce their power consumption. As a result, speed is affected, and data reliability becomes more vulnerable to noise imposing strict constraints on 6 Transistors (6T) SRAM cell design. This work focuses on 6T SRAM cell noise margin and access time analysis and modeling in addition to a new optimization methodology. The thesis consists of seven chapters including lists of contents, tables and figures as well as list of references and three appendices.
Chapter 1: contains thesis introduction, as well as literature review.
Chapter 2: presents memory background. It focuses on the SRAM architecture at the system and the bit cell level. Moreover, it shows SRAM different modes of operation including a comparison between SRAM bit cell designs at weak and strong inversion regions using 65nm CMOS technology.
Chapter 1: contains thesis introduction, as well as literature review.
Chapter 2: presents memory background. It focuses on the SRAM architecture at the system and the bit cell level. Moreover, it shows SRAM different modes of operation including a comparison between SRAM bit cell designs at weak and strong inversion regions using 65nm CMOS technology.
Other data
| Title | Low Voltage Static Random Access Memory | Other Titles | ذاكره الوصول العشوائى الساكنه ذات الجهد المنخفض | Authors | Reem Sherif El Senousy Mohamed | Issue Date | 2018 |
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