On the Verification of Configurable NoCs in Simulation and Hardware Emulation: A UVM-based Tool

Abstract

Network on Chip (NoC) has risen as an interconnection solution for the advanced digital systems, particularly for System on Chip (SoC), because of the huge number of Intellectual Properties (IPs) in the system that need to impart. Different routers and systems have been presented; subsequently the need to make a reusable verification environment to test both single routers and networks. In our thesis, we additionally propose a generic verification environment for NoC using the Universal Verification Methodology (UVM) that tests and verifies both routers and networks in an effortlessly modifiable way to fit different routers and networks.