DESIGN EXPLORATION FOR NETWORK ON CHIP BASED FPGAS: 2D AND 3D TILES TO ROUTER INTERFACE

Abstract

Abstract Due to the continuous demand for larger and more powerful chips, new blocks are added contentiously to System on Chips (SoCs), such as embedded processors, digital signal processors (DSPs), peripheral interfaces and embedded memory blocks. As the system complexity increases, the negative impact of its routing fabric increases as well. Bus-based and point-to-point interconnects become bottlenecks as they are unable to meet the system requirements. In general, they are not suitable for large systems as their performance degrades when used to connect many blocks. In addition, these interconnects normally include very long wires (global wires) to connect all parts of the chip and these global wires contribute heavily to the increased area and power consumption of the routing fabric. Field programmable gate arrays (FPGAs) are like SoCs, new blocks and components are continuously added to their architecture in order to meet the increased demand of today’s applications. With the increased number of components, the interconnect fabric starts gradually to use Network on Chips (NoCs) to overcome the problems of conventional point-to-point and bus-based interconnects. NoC consists of a network of routers connected with short links, for an FPGA block or tile to connect to another one, it only has to send its data to the nearest router instead of using global wires.

A review for several NoC designs is provided to get an idea about the current research state in this topic. The review is conducted in the context of contributions, architecture, implementation and future work. Then a comparison is held between three NoC routers to analyze the effect of changing the number of Virtual Channels (VCs), flit data width and buffer depth on the consumed area (LUTs and registers) and operating frequency. The comparison shows that the NoC architecture affects the area and maximum operating frequency of the system significantly.

As a result of the mentioned comparison, it is found that one drawback of using NoC is that increasing the router port count affects the area, power and frequency of the system significantly. In order to overcome this problem and to make the NoC approach useful in designing the next generation of FPGAs, a concentrator module or a Codec is proposed to connect between routers and multiple Tiles (FPGA basic building block). Codec reduces the effect of increasing tile count on the area, power and frequency of the routing network. In order to evaluate the effect of using Codec, a comparison is held between two networks with the same topology and size, one uses routers only and the other uses routers and Codec modules. The comparison is held in the context of area, power and maximum operating frequency. The comparison results show that the area of the Codec network is only 15% compared to the routers only network, its power consumption is 50% less, and operates with 2.5x higher frequency