EXPLORING THE SIMULATION OF DYNAMIC PARTIAL RECONFIGURATION FOR NETWORK ON CHIP (NOC)-BASED FPGA

Abstract

Abstract System-on-Chip (SoC) designs are among the most widely used designs to implement computationally data-intensive applications, which are consist of several Processing Elements (PEs) and storage elements (SEs) communicating together through the aid of a network architecture. However, several Intellectual Properties (IPs) are implemented on a single chip due to the recent developments in the fabrication process of CMOS devices.

Meanwhile, Field Programmable Gate Arrays (FPGAs) are attracting more interest to exploit SoC designs due to the constraints of Application-Specific Integrated Circuits (ASICs) such as high Non-Recurring Engineering (NRE) cost and time to market. Recently, the number of PEs is increasing to maximise functionalities and capabilities of modern SoC designs. Accordingly, communication among those PEs becomes an essential factor in the design of large-scale systems. Consequently, numerous challenges of the communication amongst those PEs, while configured on FPGAs, are raised and thus, innovative solutions are needed. Therefore, Network-on-Chip (NoC) has been adopted for FPGA to address these communication challenges.

On the other hand, Dynamic Partial Reconfiguration (DPR) of SRAM- based FPGAs becomes a remarkable feature for many applications, as DPR represents the potential to add more flexibility during runtime. Moreover, adding the DPR feature to many applications is easier than before because of the recent developments FPGA’s software designing tools such as Quartus for Intel (previously Altera) and ISE for Xilinx. On the contrary, DPR configuration technique such as Internal Configuration Access Port (ICAP) and Joint Test Action Group (JTAG) port, encounters a performance limitation because only one reconfiguration is permitted at a time.

In this thesis, a state-of-art NoC-based FPGA simulator is proposed, which supports DPR simulation. NoC-DPR simulator is used to estimate design limitations and performance degradations of using DPR for NoC-based FPGA. NoC-DPR simulator measures the reconfiguration time overhead, which caused by network’s latency, and the concurrent reconfigurations on FPGA fabric. It is proven that the overhead of reconfiguration time increases exponentially with increasing the number of concurrent reconfigurations. However, further investigations show that the network of wormhole routers with virtual channels optimises the reconfiguration time with a factor up to 4x compared to the network of wormhole routers without virtual channels. Finally, a case study is introduced to clarify the DPR performance gap between NoC-based FPGAs and conventional FPGAs.