DESIGN OF A RECONFIGURABLE NETWORK ON CHIP FOR NEXT GENERATION FPGA USINGDYNAMIC PARTIAL RECONFIGURATION

Abstract

With the vast increase in the design densities inside System-on-Chips (SoCs) every year, Network-on-Chip (NoC) design architecture is introduced as a reliable on-chip communication platform facing the challenges of complex design systems. NoC design approach is preferred over the conventional bus communication for its scalability, improved modularity, and better performance.

On the other hand, the advancement in dynamically reconfigurable Field Programmable Gate Arrays (FPGAs)allows the hardware designs to be reconfigured during runtime. Dynamic Partial Reconfiguration (DPR)adds more flexibility to hardware modules and offers better area utilization and more power optimization. Furthermore, using DPR permits the adaptive hardware algorithms to evolve based on the different applications.

Introducing the reconfigurability concept into one of the most ramping and trending design platforms like the NoC is considered a good opportunity for extracting the benefits out of the two concepts. The high flexibility and full customization of the reconfigurable NoC could open the door for a completely adaptive NoC that suits a large number of benchmarks according to the runtime requirements.The importance of reconfigurable NoCs appears with the designs intended to be dynamically reconfigurable. When the NoC is part of the design, its re-configurability gives the opportunity to operate with the best fit network to every user benchmark.

The ability to reconfigure SRAM-based FPGAs is the most powerful feature over Application Specific Integrated Circuit (ASIC) designs. DPR emphasizes this feature by increasing flexibility over runtime phase. Xilinx Virtex family of FPGAs provides four techniques to perform DPR; SelectMAP, Serial mode, JTAG, and ICAP. In this thesis, each technique is reviewed, evaluated, and tested using convolutional encoder module which is an essential block from Software Defined Radio (SDR) system.SDR as a system is chosen as it becomes the most promising application for DPR. Experiments are carried out using Xilinx Virtex 5 to measure the trade-offs between performance and area-overhead by adding reconfiguration controller on/off FPGA fabric. It is shown that the performance of each interface is independent of design resource. However,the performance is proportional only with partial reconfiguration region selection which had been chosen at the Place and Route phase.

The main objective of this thesis is to present the runtime configurability support to CONNECT NoC.Additionally, the thesisstudies the impact of this reconfigurability on the network performance with its different configuration parameters. Runtime configurability expands the flexibility of NoCs and allows a full customization to the NoCwith the dynamic reconfigurable designs. In comparison with the fixed NoCs, the runtime configurable NoCs save area by reusing a part of the network when it is not required during runtime. A reconfiguration tool is developedto assist the user in constructing the optimal network structure for every used benchmark. The reconfiguration tool requires the minimum needed throughput and the expected traffic load as inputs. The tool inputs are required to recommend the best network configuration according to the minimum area that achieves those requirements.