Injection-Locked Ring Oscillators

Abstract

This thesis discusses the analysis and the design of an injection-locked ring oscillator for forward-clocking architecture in serial-link transceivers. The injection locking mechanism is analysed and employed in the super-harmonic injection locking scheme. In this scheme, super-harmonic injection is introduced to a ring oscillator to achieve low phase noise, low rms jitter and a better figure of merit. The ring oscillator was built using Maneatis delay cells for its advantages, like the simple design, high supply/substrate noise rejection and good control over delay. Simulation results of a 130-nm CMOS design demonstrate the feasibility of the proposed design, achieving the lowest phase noise, jitter and area consumption with respect to many other designs and topologies. It operates at a frequency of 1.52 GHz, with an injection clock of 7.6 GHz. Simulation results show a 58-MHz locking range, achieved with a power consumption of 9.93 mW. Simulation results of RMS jitter, phase noise and phase deskew across a range of oscillation frequencies (1.51 GHz  1.53 GHz) are illustrated and discussed.