Charge-Steering Circuits for Low-Power Applications

Abstract

This thesis aims to study and design charge-steering (CS) circuits for different applications. The thesis is divided into two main parts design of CS circuits for high-speed wireline transceivers and the study of energy-delay curves for different types of flip-flops (FFs). The thesis consists of five chapters including lists of contents, tables and figures as well as list of references. Chapter 1 Chapter 1 gives a brief introduction to the motivation, objectives, major contributions and organization of the thesis. Chapter 2 Chapter 2 presents a literature survey for wireline transceivers and discuss the prior art for low-swing FFs. The analysis and design of low-swing FF are discussed thoroughly in this chapter. Chapter 3 Chapter 3 shows the proposed CS circuits to enhance the power efficiency of the high-speed wireline receiver. Two newly proposed CS FFs along with a CS based DFE are presented and discussed thoroughly. Chapter 4 The analysis and comparison of different FFs types are discussed in this chapter. The design variables are separated for each FF into dependent and independent design variables. The optimization using energy-delay curves using a unified methodology is introduced for both low-swing FFs and rail-to-rail FFs. Chapter 5: