.VHDL Synthesis for ASICs Applied to DLX RISC Processors

Abstract

In this thesis, a VHDL synthesizable model for AutoLogic II, is developed for a modified and unpipelined version of the 32-bit DLX RISC processor, called DLXS. This processor is taken as a case study for synthesizing complex digital AS/Cs with the VHDL language. The Mentor Graphics EDA tools are used for the synthesis, simulation, and layout generation of the DLXS processor. The CMOSN standard cell library - with technology 0.8µ - is used as a target library. A DLX test-bench is used to simulate the DLXS processor before and after synthesis to verify correctness of the synthesis operation. Due to large chip area, leading to high cost, and testing complexity of the DLXS processor, a modified 8-bit version of the ALU part of the DLXS is only sent for fabrication with the 1.2µ AMI ABN CMOS process, that is supported by the MOSIS service. This ALU is also VHDL modeled, synthesized, simulated, and placed and routed with the Mentor Graphics EDA tools, then the chip layout is converted to the CIF fabrication pattern that MOSIS accepts.