Improving the system thermal reliability using thermal-gradient-based placed heaters

Abstract

Design reliability requirements are growing rapidly to cope with design complexity and process challenges. Common design specifications are qualified against process corners, known as PVT (process, voltage, and temperature), are getting more complex. Bias, bandgap, circuit is one of the critical building blocks which compensates for both supply fluctuations and temperature variations. In these bias circuits, the incorporated temperature compensation techniques are usually based on first or second order approximations which reduce the temperature validity range. Beyond this validity range, the biasing reference voltage gets dominated by nonlinearities and becomes temperature dependent. The impact of these nonlinearities is amplified by the effect of thermal gradient across the chip which causes both soft and hard silicon failures. This work proposes an on-chip temperature sensing and holding mechanism that extends the bias temperature compensation validity range by keeping the chip in thermal equilibrium and avoiding thermal gradient and skewness. This work leverages a geometrical-based thermal symmetry and gradient verification approach that allows even placement and distribution of thermal heaters in low voltage (LV) areas to compensate for hot regions across the chip. The flow has been implemented on a voltage regulator test chip and demonstrated reliability improvements.