A 0.35 mW 8-bit 140MS/s Asynchronous Hybrid ADC for Low Energy Radio Applications

Abstract

This paper presents an asynchronous hybrid Flash-SAR ADC for low energy radio applications. A new technique is introduced for decreasing the number of comparators of the Flash ADC stage in a Flash-SAR ADC. This technique is applied to the proposed hybrid ADC which is an 8-bit ADC consisting of a 3-bit Flash ADC and a 6-bit SAR ADC with one redundant bit. The Flash ADC helps in reducing the number of conversion cycles of the SAR ADC allowing a faster sampling frequency for the ADC. The reduction in the number of comparators of the Flash ADC helps in a significant reduction in power consumption. The proposed hybrid ADC was implemented in 65-nm CMOS technology and achieves 46.63 dB SNDR at 140 MS/s with only 0.35 mW power consumption.