ANtarctica: ANalog Thermal Aware, with Reduced Constraint, Technique for Checking Analysis

Abstract

With the growing complexity in design requirements and the manufacturing process, more checks are needed to accomplish design tape-out with faster turn-Around-Time and better quality covering physical, circuit and reliability verification flows. Thermal/power profiling and analysis are examples of verification flows that became more critical for performance, yield and reliability especially when it comes to power consumption, mean-Time-To-failure (MTTF) and aging. Commercial thermal/power analysis solutions mainly focus on high-level packaging (e.g. for 3DIC) and low-level back-end layouts on the digital front (e.g.Thermal/power analysis such as clock gating) leaving the analog domain in critical condition. The analog sensitivity, matching and reliability requirements raise the need for achieving thermal matching and thermal symmetry while resolving thermal hotspots. This work proposes an electrical-based geometrical flow that aims at performing thermal/power-like analysis early in the design phase. It allows early fixes for issues that are usually detected after electro-Thermal simulations or expensive post-silicon analysis. The proposed flow is prototyped to generate heat maps for hotspot identification and thermal symmetry mismatch analysis in addition to an electrical front-end constraint reduction mechanism that optimizes for a full chip processing with reasonable performance.