Low-ripple PFM Buck Converter Employing Background Calibration

Abstract

This paper presents a background calibration technique to adapt the inductor peak current of Pulse Frequency Modulation (PFM) buck converters across different load, supply and external components values. The design minimizes the idle-state time and achieves high power efficiency results while sustaining Discontinuous Conduction Mode (DCM) operation. The proposed feedback circuit compares the idle-state time to a reference idle time and updates inductor peak current value in the next switching cycle using simple logic. A replica circuit matched to the PMOS switch is introduced to generate a constant inductor peak current regardless inductance, input and output voltage values. The design is implemented in UMC130nm technology from a 1.4V to 3.6V input supply. This regulator handles a wider inductor values from 1μH to 4.7μH while ensuring efficiency above 88%. The voltage ripple magnitude is minimized across all the load range from 5mA to 100mA while its variations are 70% lower than the other conventional techniques.