A low-jitter video clock recovery circuit

Abstract

Clock recovery is a key ingredient in any video system. This paper presents a novel clock recovery structure that utilizes a new digital loop that augments the well-known fractional phase locked loop. This clock data recovery achieves the desired functionality for any video system with very small jitter attributes and with multiple output phases without using off-chip components. The proposed design allows for simple dynamic control of loop gain for the digital loop. ©2010 IEEE.