A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets
Klemmer, Nikolaus; Hegazi, Emad;
Abstract
A 14-bit analog-to-digital converter (ADC) design for GSM/GPRS/EDGE handsets is implemented in 0.25 μm CMOS. The measured SNR/SNDR/DR is 85.2/84.1/88 dB respectively. The modulator and the clock generator consume 1.05 mA from 2.7 V supply. A delay-locked-loop (DLL)-based bias scheme is implemented to guarantee that amplifier slewing takes a fixed percentage of the clock cycle over process corners, temperature, and clock frequency. The proposed biasing scheme is shown to minimize settling error variations and contain design margins. © 2006 IEEE.
Other data
| Title | A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets | Authors | Klemmer, Nikolaus; Hegazi, Emad | Keywords | Analog-to-digital converter (ADC) | Bias calibration | Delta sigma | Noise | Switched capacitor | Issue Date | 1-Feb-2006 | Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | Journal | IEEE Journal of Solid-State Circuits | ISSN | 00189200 | DOI | 10.1109/JSSC.2005.862355 | Scopus ID | 2-s2.0-31644449721 | Web of science ID | WOS:000235372800003 |
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