A hardware design and implementation for accelerating motion detection using (System on Chip) SOC

Abstract

Motion detection is a key role in video surveillance, as a result of using a high-resolution camera in motion detection which produces a high definition video streaming, it's difficult to process this huge amount of data in real time on a serial processor. System on chip (SOC) addressed this problem by combining FPGA and serial processor on one chip that can be used to develop a complex heterogeneous system. Therefore, we can use the power of FPGA parallel processing technique in accelerating the image processing algorithms. In this paper, we present a hardware design and implementation for accelerating motion detection and optimizing the FPGA resources. The experimental result of this design is presented and detailed.