Fast and accurate technique for comparator offset voltage simulation

Abstract

A universal simulation technique for determining comparator offset voltage is proposed. The proposed technique uses a modified successive approximation algorithm to determine the offset voltage in short simulation time while preserving accuracy and precision. The comparator's input waveform is selectively reset to provide a quasi-monotonic stimulus to the comparator; thus, comparator's hysteresis can be identified and accurately determined. The technique is implemented in a parameterized Verilog-A model and can be applied to any type of comparator. Monte Carlo simulation of StrongArm dynamic comparator implemented in 180 nm CMOS technology shows that the proposed technique achieves 45 × speed-up in simulation time compared to the standard linear search, while achieving similar accuracy.