Charge-Steering Flip-Flop for Ultra-High-Speed Wireline Applications

Abstract

Flip-Flops (FFs) are the main building block in all of the digital circuits. FFs are required to operate at high frequency while having low power consumption. Charge-Steering (CS) FFs have superiority over both rail-to-rail and current-mode-logic FFs. However, CS FFs suffer from at least one of the following issues; inter-symbol interference (ISI), require quadrature clocking system, provide no gain, and/or output isn't valid for the entire clock cycle. This paper presents a CS FF that solves all of the above-mentioned issues. The proposed CS FF, implemented in a 65-nm CMOS technology, is able to work at data rates beyond 25-Gb/s that can be used in 50-Gb/s wireline transceivers employing half-rate architectures. The proposed CS FF consumes only 520 μW from a 1-V supply at 25-Gb/s data rate.