Large Scale Circuit Analysis: An Analog signature-based partitioning approach

Abstract

VLSI design and fabrication process requirements are evolving specially when it comes to turn-around time, quality of results and the associated database size. Traditional database optimization techniques aim at leveraging database parallel processing. However, the input database optimization is still lagging due to dependency on the geometrical aspect of the design without leveraging its electrical front-end counterpart. Moreover, some design stages such as thermal verification requires a database that consolidates geometrical, electrical, and thermal data. Thermal analysis and verification of SoCs have become critical steps in IC design cycle from the reliability aspect for most of the design types. Commercial and traditional mechanisms are known to be slow, complex, and indicate the fixes very late in the design cycle with a big focus on the packaging level and a relatively small focus for the design analog back-end layouts which is critical for applications such as Automotive, 5G, and IoT. This thesis demonstrates a new thermal verification flow that leverages an electrical-aware data mining scheme. The proposed scheme constructs an optimized database by adopting an electrical signature to drive the database partitioning-clustering mechanism. The optimized database contains electrical-aware data clusters that eliminate redundancy hence improve runtime, accuracy, and allow for extended validation for analog sensitivity, matching, and compliance with reliability guidelines such as identifying thermal hotspots, verifying thermal symmetry and thermal gradient. The proposed verification flow has been used to drive interactive thermal hotspots fixing in early design phases. With the objective of reducing the peak thermal/power density in hotspots and achieving thermal symmetry, the flow allows optimizing heat source locations across the chip extent. The proposed flow permits benefits that can be readily realized as it provides fast, interactive, and actionable feedback to optimize the placement of the critical devices. The flow has been proven on small as well as large scale analog designs covering turn-around time (TaT), ease of use (EoU), and quality of results (QoR) aspects. The results have been compared to the state-of-the-art techniques and results from designs with same complexity and size.