Hyprid Analog-to-Digital Converter for Low Power Applications

Abstract

Noise Shaping Successive-Approximation Analog-to-Digital Converters (NS SAR ADCs) are one of the most trending ADC topologies that are heavily researched in recent years. This high interest is attributed to the advantages of the NS SAR architecture that combines the merits of SAR and Σ∆ Converters. NS SAR ADCs are capable of achieving low power and high resolution at the same time. However, the implementation, of a NS SAR loop filter in a passive or active form, imposes some design challenges related to the power dissipation, technology scaling, performance, and robustness against PVT variations. The most critical block in a NS SAR ADC is the integrator that performs the residue integration. To obtain aggressive and accurate noise transfer function (NTF), a closed loop OTA can be used and will be power inefficient because of the static current consumed. It will be robust against PVT but it does not scale easily. A passive filter can be used instead but will give less aggressive NTF and will do less suppression to comparator noise as the passive gain is limited. Its gain will vary across PVT. This thesis proposes an inverter-based NS SAR ADC implementation that alle¬viates these design challenges. This will keep the power efficiency of the integrator and will be scaled easily. The inverter-based OTA is self-tuned to achieve the required specs across PVT variation. A system analysis of the different factors of a NS SAR ADC is performed show¬ing the critical design specs and system design guidelines is set to ease the choice of NS filter. The proposed implementation is used to design a NS SAR ADC with cascaded FIR-IIR loop filter in 28-nm CMOS technology achieving an SNDR of 70.03 dB for an 11.25 MHz signal bandwidth, consuming 0.64 mW.