DESIGN OF BUFFER-LESS THREE DIMENSIONAL (3D) NETWORK ON CHIP (NoC) ROUTERS

Abstract

In this work brief introduction to network on chip is included. Followed by an introduction to the architecture of CONNECT and related work in buffer-less router designs. Next, this work presents Modified CONNECT buffer-less router architecture that targets FPGA. A discussion on 3-dimensional network pros and cons is introduced followed by simulations of

3D-Modified CONNECT. Later, a brief study is introduced that discusses the optimum size and feature of 3D NoC. Finally, A CAD tool is presented that summarize the work and enables the user to configure different buffer-less 3D NoCs.