A PIPELINE ADC USING ENHANCED-LINEARITY RING-AMPLIFIER

Abstract

This thesis proposes a slew rate enhancement technique which solves the fundamental trade-off between speed and stability. The proposal is to use a rail-to-rail controlled feedforward path to be used in parallel with an original ring amplifier. This feedforward path boosts the linearity of the amplifier significantly without any stability degradation. The linearity improvement is achieved by enhancing the slew rate of the used amplifier while minimizing the overhead current consumption. Thus, using this feedforward path enhances the linearity for almost the same current consumption, hence reducing the overall system figure of merit (FoM). The core idea of the thesis has been verified using M-DAC architecture with unity closed loop gain. The proposal enhances the total harmonic distortion by 10dB while reducing the overall FoM by more than half compared to state-of-the-art techniques. Then, a 10-bit 1.5-bit/stage pipeline ADC has been implemented using this adaptive ring-amplifier. The full system has been implemented using TSMC 65nm CMOS technology and 0.9V supply voltage.