An Automatic Generation of NoC Architectures: An Application-Mapping Approach

Abstract

In Multi-Processor System-on-Chips (MPSoC)s, On-chip interconnection standouts among obtaining greater computing capabilities, maintaining high processing speeds, and highperformance architectures. Emulation and verification are essential to assess the correctness and performance of MPSoC architectures. Manycore architectures with thousands of processing tiles create interesting challenges to maintain high processing speeds with satisfiable energy dissipation. One of these architectures, Networks-on-Chips (NoC) proved to be a suitable candidate to achieve that target goal. To have a successful realization of such systems, we need a fast and robust emulation platform. In our thesis, we present a highly scalable, flexible hardware-software emulation framework, which is designed based on the open-source RISC-V Instruction Set Architecture (ISA) element to provide real traffic patterns to the network implemented on an emulator. This framework is established to auto-generate and fully build NoC based MPSoC systems through which NoCs, built upon various types of network topologies, routing algorithms, traffic patterns (TPs), buffer sizes, and flow control schemes can be validated and evaluated. The Universal Verification Methodology (UVM) environment will be auto-generated depending on the selected network configurations to suitably explore, evaluate, and compare a wide range of NoC solutions with variant network parameters. This framework generates a synthesizable RTL that can be used in both ASIC and FPGA implementations. We propose a generic UVM environment for the MPSoCs based on our scalable and generic NoC emulation framework using the Testbench-Xpress (TBX) technology to allow the designers to explore and detect all network’ failures. This UVM environment tests the throughput of different NoCs configuration, checks the routing paths, validates the transmitted packet data and the received one in each router port, and also the collector port of the Processor Element (PE). We are measuring our configurable framework by providing different NoC routers architectures to support different measurements through different network parameters; topology, network size, network dimension, Traffic Pattern (TP), routing algorithms, flow control, number of Virtual Channels (VCs), buffer size, buffer management, flit size, arbiter type, maximum payload length, and VC allocation type. We will discuss all the used routers architectures; Daniel’s NoC router, distributed/centralized networks-based conventional buffering, round-robin flexible buffering routers (XYZ routing, west-first dynamic routing, and negative-first dynamic routing) algorithms, and distributed/centralized network-based virtual channel conventional buffering router architectures to x