Injection Locked Oscillators

Abstract

Clock and frequency synthesizers are essential block in any wireless or wireline transceivers also they play a critical role in the performance of any micro- processor. The frequency synthesizers should meet the stringent requirements imposed by the modern systems in terms of low jitter, low power and small area. Conventionally, the frequency synthesizers and clock multipliers are re- alized using phase locked loops (PLLs). However, the low jitter requirement is difficult to achieve in PLLs without high power consumption and large area. New architectures and techniques are investigated in literature to overcome this tradeoff. This thesis aims to investigate and design a low-jitter clock multiplier using injection locking which is a promising technique that can overcome the trade- offs in the other conventional clock multipliers. A ring-based injection-locked oscillator with continuous frequency-tracking loop (FTL) is proposed that gen- erates an output clock from 2.4 GHz to 2.8 GHz. The FTL maintains the oscillator inside its lock range across process, supply and temperature (PVT) variations. A reference frequency quadrupler is proposed with a duty cycle

correction circuit that lowers the deterministic jitter of its output clock. A high multiplication factor of 56 is achieved using the frequency quadrupler with the injection locked clock multiplier. Finally, the proposed design is im- plemented using 130-nm CMOS process and achieves a high figure-of-merit (FoM) compared to the state of art designs.