Electro-Thermo-Mechanical Modeling of Relaxed-Stress TSVs

Abstract

3D integration has emerged as an effective way to improve the performance of microelectronic devices. Compared with 2D classical schemes, 3D integration has a lot of benefits such as shorter interconnection, heterogeneous integration, and power consumption reduction. In this regard, Through Silicon Vias (TSVs) provide the vertical connection between stacked chips. They minimize the interconnect paths leading to a reduction in parasitic capacitance and resistance and offer small packaging sizes. However, TSV interconnects face some challenges in design and fabrication. Some of these issues are via etching and filling, thermal management, and floor planning. Due to differences in the coefficient of thermal expansion (CTE) between the bulk and the TSV filling material, stresses are generated in the bulk around the TSV during thermal cycles. These generated stresses may lead to damage or crack of the wafer and interfacial delamination of TSV. Moreover, the mobility of carriers is changed due to the generated stresses. There would be an area around TSV where the transistors and active elements should be put away. This area is called keep out zone (KOZ) where the stresses are very high and affect the reliability of transistor performance. Tunnel field effect transistor (TFET) is proposed as a good alternative to MOSFET transistors where the current is mainly due to band to band tunneling phenomena instead of thermionic emission as in traditional MOSFETs. TFET has advantages over MOSFET of low leakage current, low power supply, and a better ION/IOFF ratio. However, some challenges face the