Reference Oscillators for RF-PLL Systems

Abstract

Recently, low-power circuit design gains a big momentum as it considered as a key enabler for different applications, especially Internet of Things (IoT) systems. Moreover, low-power circuit design allows reducing the battery size by reducing the needed power consumption, which accordingly reduces the area/cost of these systems and enhance the battery lifetime. Typically, the receiver (RX) and the Transmitter (TX) within the wireless communication systems consume a significant fraction of power from the whole power consumption. Phased Locked Loop (PLL), which is a basic building block in any wireless communication systems for a precise clock generation, dominates the power consumption of the RX/TX. Moreover, the frequency divider and the Voltage-Controlled Oscillator (VCO) within the PLL dominates the power consumption of the PLL. Consequently, in this thesis, a low-power, low area Phased Locked Loop is presented using 130nm CMOS technology. The proposed frequency synthesizer exploits the